Processor Fundamentals: past paper questions
Real questions on processor fundamentals
The newest 20 of 127 written questions. Open one to see it on the real paper.
- 9618/11 · October/November 2025 · Q1a(iii)[2]
Convert the 12-bit two’s complement binary integer into denary. 111110111100 Working Show your working.
See it on the paper → - 9618/11 · October/November 2025 · Q1b(i)[1]
The following binary addition is performed using 8-bit registers. Complete the calculation using binary addition. 1 0 1 1 0 0 1 1 + 0 1 1 1 1 0 0 0
See it on the paper → - 9618/11 · October/November 2025 · Q1b(ii)[2]
Name and describe the error that can occur when binary addition is performed.
See it on the paper → - 9618/11 · October/November 2025 · Q4a[1]
1 1 1 1 0 Write a bit manipulation instruction that uses a binary shift to change the contents of the ACC to: 0 1 1 1 1 0 0 0 Instruction 0 (a) The ACC currently contains the following positive binary integer:
See it on the paper → - 9618/11 · October/November 2025 · Q6a[2]
The processor uses several registers, including the Accumulator (ACC) and the Current Instruction Register (CIR). Complete the table by describing the role of each register. Register ACC Role
See it on the paper → - 9618/11 · October/November 2025 · Q6b[2]
Increasing the number of cores in a processor can affect the performance of a computer. Describe the drawbacks of increasing the number of cores in a processor.
See it on the paper → - 9618/12 · October/November 2025 · Q3a(i)[1]
State what is meant by relative addressing.
See it on the paper → - 9618/12 · October/November 2025 · Q3a(ii)[2]
Registers such as the Accumulator (ACC) and the Index Register (IX) are used in the CPU. Identify two special purpose registers used in the CPU. Do not include the ACC or IX in your answers.
See it on the paper → - 9618/12 · October/November 2025 · Q3b[3]
The following table shows part of the instruction set for a processor. The processor has two registers: the ACC and an IX. Instruction Explanation Operand LDM #n Immediate addressing. Load the number n to ACC LDD <address> Direct addressing. Load the contents of the location at the given address to ACC LDI <address> In...
See it on the paper → - 9618/12 · October/November 2025 · Q3c[4]
A student buys a new computer. The table shows the specifications of the old computer and the new computer. Old computer New computer 1.8 GHz dual core processor 2.3 GHz dual core processor 16 MB cache 32 MB cache Explain why increasing the clock speed and increasing the cache memory will improve the performance of the...
See it on the paper → - 9618/13 · October/November 2025 · Q2b[1]
Convert the denary number –108 into a 12‑bit two’s complement binary number.
See it on the paper → - 9618/13 · October/November 2025 · Q2c[1]
A three‑place arithmetic shift to the right is performed on the following two’s complement negative integer. Show the result of this arithmetic shift. 10010011
See it on the paper → - 9618/13 · October/November 2025 · Q6a[4]
Complete the table by writing the contents of the ACC after the execution of each instruction. Current contents of the ACC Instruction 0000 1111 AND 101 0000 0000 LDM #100 0000 0001 XOR &F1 0001 0001 CMP 101 Contents of the ACC after the execution of the instruction
See it on the paper → - 9618/13 · October/November 2025 · Q6b[4]
The Von Neumann model for a computer system uses registers. Describe the role of the Memory Address Register (MAR) and Memory Data Register (MDR) in the fetch‑execute (F‑E) cycle.
See it on the paper → - 9618/31 · October/November 2025 · Q11a[6]
Write assembly language code, using only the given instruction set to: • • • store the denary value 100 as a named constant subtract the constant from the value contained in address 632 store the result in variable Answer. Show the initialisation of the constant and Answer in the table provided. Label Contents
See it on the paper → - 9618/31 · October/November 2025 · Q11b[1]
The address 632 contains the value 45. State the value of Answer after the code described in part (a) has executed.
See it on the paper → - 9618/32 · October/November 2025 · Q5a[2]
Describe how interrupt handling is used in low-level scheduling.
See it on the paper → - 9618/33 · October/November 2025 · Q13[7]
The table shows assembly language instructions for a processor that has one register, the Accumulator (ACC). Instruction Opcode Operand LDM #n Explanation Load the number n to the ACC LDD <address> LDI <address> ADD <address> Load the contents of the location at the given address to the ACC The address to be used is at...
See it on the paper → - 9618/11 · May/June 2025 · Q8b(i)[1]
Write the bit manipulation instruction that can be used to set the least significant bit to 1 in an 8‑bit register. All other bits must remain unchanged. The instruction needs to work on a register that contains any 8‑bit binary number.
See it on the paper → - 9618/11 · May/June 2025 · Q8b(ii)[1]
The ACC currently contains the following binary value. 0 1 0 1 0 1 0 1 Write the result after the instruction XOR &FE is run.
See it on the paper →
What examiners said
Candidates were given specific values for the clock speed of the computer. Their answers were expected to refer the values given. Some candidates need to take care in their use of terminology. Instruction was seen frequently instead of F-E cycle.
— Examiner report, October/November 2023, 9618/11 Q5(c)(i) (Cambridge)
There were a small number of excellent answers to this question. Many candidates need to understand that when using multiple cores, each core has its own processor and that there is a need for communication between these individual processors. Answers such as ‘there will be an additional load on the processor’ were seen frequently.
— Examiner report, October/November 2023, 9618/11 Q5(c)(ii) (Cambridge)
This question was generally not answered well. Many candidates need to improve their understanding of the purpose of each pass of a two-pass compiler.
— Examiner report, October/November 2023, 9618/11 Q8(a) (Cambridge)
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